1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a semiconductor device formed on an SOI (Silicon On Insulator) substrate, having a standby mode and an active mode.
2. Description of the Background Art
FIG. 13 is a circuit diagram showing a structure of a CMOS inverter 70 of a conventional integrated semiconductor device (DRAM, SRAM, and the like) formed on an SOI substrate. Referring to FIG. 13, CMOS inverter 70 includes an input node N71, an output node N72, a p channel MOS transistor 71, and an n channel MOS transistor 72. An input signal Vin is applied to input node N71. An output signal Vout is provided from output node N72. P channel MOS transistor 71 has its gate connected to input node 71, a source receiving a power supply potential Vcc, and a drain connected to output node N72. N channel MOS transistor has its gate connected to input node N71, its drain connected to output node N72, and its source grounded. The bodies of MOS transistor 71 and 72 are both set to a floating state.
FIG. 14A is a partially broken away plan view of a device structure of n channel MOS transistor 72 shown in FIG. 13. FIG. 14B is a sectional view of n channel MOS transistor 72 of FIG. 14A taken along line X-X'. Referring to FIGS. 14A and 14B, n channel MOS transistor 72 is formed on SiO substrate 73. SOI substrate 73 includes a silicon substrate 74, an SiO buried oxide layer 75 and a p.sup.- type silicon layer 76 stacked thereon. The element region of n channel MOS transistor 72 is isolated from other element regions by an SiO insulation layer 77 which is an oxidized p.sup.- type silicon layer 76.
A gate electrode 81 is formed above the center portion of the element region with a gate oxide film therebetween (not shown). The portion of p.sup.- type silicon layer 76 covered by gate electrode 81 is a body region 82. An n.sup.+ type drain region 83 and an n.sup.+ type source region 84 are formed at one side and the other side, respectively, of gate electrode 81. Gate electrode 81 is connected to input node N71. N.sup.+ type drain region 83 is connected output node N72 via a contact hole CH. N.sup.+ type source region 84 is grounded via contact hole CH. The device structure of p channel MOS transistor 71 is similar to that of n channel MOS transistor 72 provided that the p type and the n type are opposite.
The operation of CMOS inverter 70 shown in FIGS. 13, 14A and 14B will be described hereinafter. In a standby mode period where input signal Vin attains an L level (ground level Vss), p channel MOS transistor 71 is rendered conductive and n channel MOS transistor 72 is rendered non-conductive, whereby output signal Vout attains an H level (power supply level Vcc). When input signal Vin rises to an H level in an active mode period, p channel MOS transistor 71 is rendered non-conductive, and n channel MOS transistor 72 is rendered conductive, whereby output signal Vout attains an L level.
In such integrated semiconductor devices, research to reduce power supply voltage is in progress together with increase in the integration density. It is therefore necessary to lower the threshold voltage of the MOS transistor forming the integrated semiconductor device to increase the driving capability thereof so that the integrated semiconductor device can operate at high speed under low power supply voltage.
However, reduction of the threshold voltage of the MOS transistor corresponding to the power supply voltage will increase the subthreshold leakage current I.sub.L therein. It is not possible to reduce the threshold voltage of the MOS transistor corresponding to reduction of the power supply voltage. Difficulty in increasing the performance of an integrated semiconductor device, particularly increasing the operation rate, is expected. Such problems are pointed out in, for example, 1993 Symposium on VLSI Circuit Digest of Technical Papers, pp. 47-48 and pp. 83-84.
In n channel MOS transistor 72 of CMOS inverter 70 shown in FIGS. 13, 14A and 14B, reduction in the threshold voltage will cause increase in the junction leakage current from n.sup.+ type drain region 83 into p.sup.- type body region 82 during a standby period. This causes increase in the potential of p.sup.- type body region 82, whereby the threshold leakage current I.sub.L of n channel MOS transistor 72 is increased. This phenomenon is pointed out in, for example, 1995 Symposium on VLSI Technology Digest of Technical Papers, pp. 141-142.
One method of reducing subthreshold leakage current I.sub.L is to fix the potential of p.sup.- type body region 82 of n channel MOS transistor 72. To implement this method, a T-shaped gate electrode 81' is provided, and a p.sup.+ type contact region 85 is provided so as to contact p.sup.- type body region 82' covered with gate electrode 81, as shown in FIG. 16. The potential of p.sup.- type body region 82' can be prevented from increasing by applying a constant substrate potential to p.sup.+ type contact region 85 via contact hole CH, whereby the threshold leakage I.sub.L can be reduced.
However, there was a problem that the layout area for providing p.sup.+ type contact hole region 85 is increased in this method. There was also a problem that the operation speed is delayed due to increase of the capacitance between p.sup.- type body region 82 and n.sup.+ drain and source regions 83 and 84.